FPGA Based Logic Analyzer
The project includes the actual analyzer in VHDL (for Spartan 3 FPGA) and a PC Software for the end user. The design employs a FPGA board that can be obtained easily.
Features
16 channels at 200MHz sampling rate
32 channels up to 100MHz sampling rate
state analysis up to 50MHz using external clock
256KSamples memory
noise filter
complex serial and parallel trigger with four stages
externally available sampling clock to drive add-ons (like ADCs)
connects via EIA232/RS232 (works with usb to serial adapters)
Java based viewing software (see PC Client for details)
I2C & SPI protocol analysis
| FPGA Based Logic Analyzer at www.sump.org |
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